1. Technical Field
The embodiments described herein generally relates to debugging systems and processes and in particular to debugging of devices having a cache-based hierarchical memory system.
2. Description of the Related Art
A large number of processing devices/systems that process data/instructions that are stored and/or retrieved from a memory are designed with a memory hierarchy that includes one or more levels of caches. With some of these devices/systems, the memory hierarchy is hardware coherent (i.e., coherency enforced by hardware design), while other devices/systems comprise non-coherent memory hierarchy. During conventional debugging operations involving such devices/systems where the cache(s) are not hardware coherent, the debugger has no non-intrusive, efficient way of determining which caches actually contain the cache line of data/instructions associated with the particular transaction address, and the debugger thus causes each cache controller to each perform a full scale address lookup within the respective cache to determine which caches contain the specific information associated with the transaction address. When performing debug operations that include updating the memory window of the debugger, the process for obtaining the required information about the caches within the memory hierarchy requires complex address lookups. If the debugger decides to bypass the complex lookup and read the cache directly, the debugger access is intrusive and can corrupt the entries within the cache. With these conventional methods, debugger modifications to memory (e.g., to install breakpoints, or modify memory) also take a significant length of time to return the requested information. Also, when the debugger wants to modify specific locations storing information associated with a specific transaction address, the debugger encounters the delays inherent with the conventional, full cache lookup mechanisms, slowing down the debug process.